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[Other] Verilogexample

Description: Verilog.pdf。有Verilog的大量范例。适合于想动手设计芯片的人。-Verilog.pdf. Verilog is a large number of examples. Suited to fight in the chip design.
Platform: | Size: 113664 | Author: 苗权 | Hits:

[VHDL-FPGA-Verilog] NumClock

Description: 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。-based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design
Platform: | Size: 23552 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] cmos_FPGA

Description: 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
Platform: | Size: 1024 | Author: margie | Hits:

[VHDL-FPGA-Verilog] !061210[1].pdf

Description: 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片-FPGA-based hardware and software asynchronous FIFO to achieve, through the Verilog programming downloaded to the FPGA chip after
Platform: | Size: 241664 | Author: youren | Hits:

[VHDL-FPGA-Verilog] VCDwtHDLV

Description: < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘-<Large RISC processor design- Verilog design language used to describe VLSI chip>> CD-ROM
Platform: | Size: 874496 | Author: wiyn | Hits:

[SCM] DDS

Description: 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation
Platform: | Size: 2745344 | Author: 张新 | Hits:

[MPI] Uart_16550_Verilog_Source

Description: UART_16550_verilogHDL源程序，用在lattice芯片上面运行，保证能用的好资料-UART_16550_verilogHDL source, lattice chip used in the above operation can be used to ensure good information
Platform: | Size: 472064 | Author: 成刚 | Hits:

[VHDL-FPGA-Verilog] 2C35F672_FFT

Description: 在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
Platform: | Size: 474112 | Author: lovenevol | Hits:

[SCM] FPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Platform: | Size: 1371136 | Author: haoren | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:

[Other Embeded program] I2C_extender

Description: verilog编写，将I2C串行数据转化为并行数据的功能模块，类似于PCF8574芯片的功能。以后不用买另外的芯片就可以直接将并行数据连到I2C总线上了-Verilog prepared to I2C serial data into parallel data of the function modules, similar to the function of PCF8574 chip. After the chips do not have to buy another can be connected directly to the parallel data to the I2C bus on the
Platform: | Size: 1024 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:

[Other Embeded program] USB2.0_Slave_FIFO_ASync

Description: This an USB2.0 chip CY7C68013 Configuraion Example for Slave FIFO mode with "async" mode.
Platform: | Size: 123904 | Author: MyName | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[VHDL-FPGA-Verilog] lctl_1.2

Description: CPLD的例子程序1,EPM7128芯片,ISA总线-Examples of CPLD procedures 1, EPM7128 chip, ISA Bus
Platform: | Size: 217088 | Author: Sean Cheung | Hits:

[VHDL-FPGA-Verilog] v2.1_ok

Description: CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用-Examples of CPLD procedures 2, EPM7064 chip, PC104 expansion cards application
Platform: | Size: 260096 | Author: Sean Cheung | Hits:

[MPI] pci_core_verilog

Description: PCI-master的核，verilog语言，经测试，可完成芯片的综合及布线-PCI-master s nuclear, verilog language, by testing, to be completed by the integrated chip and wiring
Platform: | Size: 216064 | Author: 伊路发 | Hits:

[Other Embeded program] hdb3

Description: hdb3的发送端源代码，采用verilog可综合格式书写。已经在多款fpga和cpld芯片成功综合实现。-HDB3 sending client source code, Verilog can be used to write an integrated format. Has been in several FPGA and CPLD chip integrated to achieve success.
Platform: | Size: 1024 | Author: frankey | Hits:

[VHDL-FPGA-Verilog] AD9852

Description: 数字频率合成器芯片AD9852 的配置文件，HDL级的Verilog代码-DDS chip AD9852 profile, HDL-level Verilog code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[SCM] adc

Description: 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。-The preparation of Verilog code box on the use of experimental A/D chip to complete analog-digital conversion. Input voltage provided by the experimental box, and its amplitude in the 0 ~ 5V between changes in control by potentiometer. Output signal shows that the value of analog voltage input from a digital display for two BCD code of the form.
Platform: | Size: 22528 | Author: Ericwhu | Hits:
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